1. Field of the Invention
The invention relates to superconductive integrated circuits and more particularly to tunneling junctions adapted to replace deposited thin film resistors. The invention is particularly applicable to Josephson integrated circuits with multiple tunneling junctions.
2. Description of the Prior Art
In the manufacture of many integrated circuits, particularly those incorporating Josephson junctions, it is often desirable to form resistive elements by depositing a metallic layer upon an insulating surface. By means of masked etching or lift off processing the desired geometry of the thin film material is obtained. The film material used must exhibit resistive properties when operated at superconducting temperatures. Such materials as gold-indium alloy, copper-germanium alloy, and molybdenum have been used in the prior art.
One problem observed in the prior art is that where the substrate includes steep or re-entrant angles, it is difficult to deposit layers of substantially uniform thickness. Further, for some applications, such as on a power bus, resistance values must conform to the desired critical currents of the Josephson junctions. Where the junction parameters vary over the substrate, adjustment of the resistance values may be desirable. In a multilayer structure, this imposes substantial practical problems and requires additional processing steps. Where relatively high resistance values are required, a thin resistor of extended length is required. Such a resistor may exhibit undesirable inductance, as well as consume appreciable circuit area. Further, undesired parasitic contact resistance may be experienced at the interface between the resistor and superconductive layers.
Since the specific resistance for a given material is fixed, resistance is varied by choosing appropriate lengths and widths over a relatively narrow range of deposit thicknesses. Limitations of choice of suitable resistive materials dictate that substantial areas are required to define values of resistors most commonly used in Josephson junctions, substantially exceeding the dimensions of the junctions themselves. These values may range from less than 0.3 ohm to greater than 30 ohms. In the prior art, for example, a resistor of the order of 30 ohms formed from material with a sheet resistance of 2 ohms/square would require an area of 93.75.mu.m.sup.2 compared with a typical junction area of 6.25 .mu.m.sup.2, representing a ratio of 15:1. For a multiple junction application, as in a 1:2:1 interferometer, for example, a multiplicity of such resistive elements is required, with consequent consumption of chip area.
It is also noted that Josephson logic gates generally have low gain and therefore small operating margins. Resistive elements are a necessary part of these logic gates and as has been noted herein the values of the resistances are difficult to control in fabrication. Nevertheless, close control of such resistance is critical. In general, where the range of resistance values is closely controlled, an active Josephson device will permit correct operation of the gates over a relatively wide possible range of parameters.
Three important parameters of Josephson devices are the critical current I.sub.c, normal resistance R.sub.N, and the sub-gap resistance R.sub.S. The product of I.sub.c and R.sub.S is commonly referred to as V.sub.m. The sub-gap resistance R.sub.S is generally not a constant but varies with the applied voltage and is conventionally measured at a particular sub-gap voltage of the order of 1.5-2.0 mV as appropriate for the particular logic gate in which the devices are incorporated. Thus, for example, the sub-gap resistance may be conveniently measured at V.sub.g 2, where V.sub.g is the gap voltage of the junction. The normal resistance is determined by the slope of the I-V curve above V.sub.g. The I.sub.c R.sub.N product and V.sub.m are generally well controlled across a wafer with good control of the fabrication techniques. However, local variations in lithography due to imperfect masks, variations in exposure or photoresist thickness, etc. can change the device area and thereby change I.sub.c and the corresponding values of R.sub.N and R.sub.S across the wafer. Systematic variations may also occur across a wafer because of variations in the barrier thickness. It has been found that such barrier formation variations are present even in the most highly developed formation techniques, which otherwise yield acceptable devices. Such techniques include plasma oxidation and silicon barrier deposition.
Some techniques for altering the electrical properties of Josephson junctions have been previously described, although not for the purpose of fabricating resistive elements. A method for altering the low voltage resistance of a Josephson junction without affecting the zero voltage supercurrent, utilizing a proximity effect structure, was described by J. Matisoo in IBM Technical Disclosure Bulletin V16, No. 5, pp. 1437-39, Oct. 1973. Other techniques have been applied for modifying Josephson junctions in order to increase the yield. For example, indium has been deposited on the counter-electrode, which diffuses through to the tunnel barrier and increases the magnitude of the critical current. An another example, junctions have been annealed to increase critical current. While these methods can be accomplished with the required selectivity, they do not change the essential functionality of the device as a Josephson junction, and are not methods of making resistors from Josephson junctions as described herein.
The introduction of impurities into niobium electrodes as a means of preparing low resistivity resistors has also been suggested in a paper by J. C. Villegier and J. C. Veler, to be published in the Proceedings of the Applied Superconductivity Conference, Nov. 30, 1982.